The invention relates to semiconductor memory devices.
Non-volatile memories have been used for many different applications. In microprocessor or microcontroller-based systems, for example, non-volatile memory devices may store boot-up code to initialize the systems during power-up sequences. In other electronic devices, non-volatile memory devices may be used to store information that would otherwise be lost if power is removed.
One type of non-volatile memory is the electrically erasable and programmable read-only memory (EEPROM). In an EEPROM, a memory cell typically includes a memory transistor having a floating gate that is capacitively coupled to a select gate. A thin oxide layer is typically formed between the floating gate and the drain of the memory transistor. Under the influence of applied high voltages, a memory cell is programmed by Fowler-Nordheim tunneling of electrons through the thin oxide layer between the drain and floating gate of the memory transistor. Fowler-Nordheim tunneling, also referred to as cold-electron tunneling, is a quantum-mechanical effect that allows electrons to pass through an energy barrier at a silicon-silicon dioxide interface at lower energy levels than hot-electron tunneling.
Referring to FIGS. 10A and 10B, a double-polysilicon EEPROM cell is illustrated. Single-polysilicon and triple-polysilicon EEPROM cells have also been implemented with varying memory cells structures. A word line 10, in combination with doped regions 12 and 14 and a gate oxide layer 11, form an access transistor 20 (as illustrated in the equivalent circuit diagram of FIG. 10B) that is an enhancement-type n-channel metal silicon oxide field effect transistor (MOSFET). The doped region 12 is coupled to a bit line, which in turn is coupled to sensing circuitry that senses the state of the memory cell during a read cycle. A control gate 22 is stacked and separated by an insulating layer 24 above a floating gate 26 of a memory transistor 40. The control gate 22 and floating gate 26 are capacitively coupled by a coupling capacitor C.sub.C formed by electrodes 22, 26 and dielectric layer 24.
The floating gate 26 includes a protruding portion 28 at its bottom surface, which is separated from the doped region 14 by a thin oxide layer 30, which forms the dielectric layer of a thin oxide capacitor C.sub.T. The remaining oxide layer 32 surrounding the thin oxide layer 30 formed between the floating gate 26 and the substrate 34 provides the dielectric layer of a capacitor C.sub.BG. The combination of C.sub.T and C.sub.BG provides the gate capacitance of the transistor 40. As illustrated in FIG. 10B, the control gate 22 is coupled to the source of a transistor 50 (also an enhancement-type n-channel MOSFET) having a drain coupled to an ERASE line and a gate coupled to the word line 10.
To program the memory cell, the word line is driven to an elevated voltage Vpp, which may be around 16 volts, for example. The bit line 12 is also coupled to the elevated voltage Vpp, which drives the doped region 14 to a voltage that is Vpp less a threshold voltage (Vt) with body effect of the enhancement-type transistor 20 (e.g., less than around 14 V). The ERASE line is coupled to a ground voltage, which causes the control gate 22 to also be grounded. Due to the induced electric field between the doped region 14 and the control gate 22, electrons tunnel from the floating gate 26 through the thin oxide layer 30 to the doped region 14, leaving the floating gate relatively more positively charged. This shifts the threshold voltage of the memory transistor 40 in the negative direction so that during a read mode the transistor is in the on state or the logical "0" state.
In an erase operation of the illustrated conventional EEPROM cell, the word line 10 is also driven to Vpp while the bit line 12 is driven to ground. The ERASE line is set to Vpp, which drives the control gate 22 to a voltage that is Vpp less a threshold voltage (Vt) of the enhancement-type MOSFET 50. The low-to-high transition of the control gate 22 is capacitively coupled through the coupling capacitor Cc to the floating gate 26. The gate capacitance of the memory transistor 40, including C.sub.BG, counteracts this capacitively coupling to some degree, which may require a higher Vpp level to adequately capacitively couple the floating gate to an elevated level for erasing. Because the drain 14 of the storage transistor 40 is driven to ground through the transistor 20, the induced electric field between the floating gate 26 and doped region 14 causes electrons to tunnel to the floating gate 26 from the doped region 14. The threshold voltage of the memory transistor 40 shifts in the positive direction so that during a read the transistor is in the off or logical "1" state.
To read the device, the word line 10 is driven to a normal high voltage (Vcc) and the erase line may be driven to about 2 volts or more. The state of the memory cell is determined by sensing current through the transistor 20 and the bit line.
In conventional EEPROMs, the voltage level of Vpp used to program and erase memory cells is typically maintained at a relatively high level to overcome (1) threshold voltage drops associated with enhancement-type MOSFETs coupled to control access to bit lines and erase lines; and (2) the capacitively coupling effect of the memory transistor's gate capacitance counteracting the capacitively coupling of the control gate to the floating gate. The elevated voltage levels of around 16 volts, for example, may give rise to reliability issues in addition to increasing power consumption in such devices. Further, the memory cell structures of conventional EEPROMs may not be efficient for embedded applications due to manufacturing complexities and density requirements.